Designing integrated circuits to perform a user-defined function is time consuming and can extend time to market cycles. The use of standard cell libraries with automated placement and routing software tools was developed to shorten the time required to design and verify a new integrated circuit. By using predefined functional blocks that are already implemented as standard cells, the design cycle is shortened. Automated software tools can receive as input a functional description of a desired design in a schematic form and, using algorithms for cell placement and line routing, produce an integrated circuit layout that implements the schematic.
In addition, recent developments in transistor fabrication have replaced the conventional planar metal-oxide-semiconductor (MOS) FET transistor with finFET devices. By forming a three dimensional fin of semiconductor material, and fabricating metal or polysilicon gate structures over the fins, the gate length of the transistor can be longer for a given area, increasing device performance even as the semiconductor processes continue to shrink, and improving density. Standard cell libraries are now implemented using finFET transistors. However, the use of finFET transistors in the standard cell methodologies creates additional problems in verification.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.